1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the same.
2. Description of the Prior Art
As integration of a semiconductor device is improved, driving speed and current gain thereof are enhanced, but operation characteristic thereof is restricted somewhat.
FIG. 1 is a cross-sectional view showing the construction of a bipolar transistor which is fabricated by a prior art method.
This technique is that a parasitic junction capacitance of a collector 3, i.e. a parasitic junction capacitance between a substrate 1 and a buried collector 2, is reduced and a size of a bipolar transistor is further small.
In FIG. 1, reference numeral 6 indicates an insulating layer, reference numeral 7 indicates a base region, and reference numerals 8 and 9 indicate an emitter region and an electrode, respectively.
In the bipolar transistor of FIG. 1, since the base region 7 is wide and the emitter and base regions 8, 7 are jointed with each other at high concentration, there arises the problem that a power consumption is large.
Also, to enhance operation characteristic, the construction of a pillar bipolar transistor is disclosed in Europe Patent Application No. 84113062.8, as shown in FIG. 2.
With reference to FIG. 2, the method for fabricating the disclosed pillar bipolar transistor comprises the steps of selectively etching a single crystal semiconductor substrate 11 to form pillars therein, forming an emitter region 18, a base region 17, a collector region 13 and collector sinker region 15 in the pillars, isolating active regions by a buried insulating layer 16, and forming a polysilicon layer 14 as an extrinsic base region at both sides of one of the pillars to complete fabrication of a pillar bipolar transistor.
In the prior art pillar bipolar transistor fabricated by the above method, however, since the polysilicon layer 14 is connected with both sides of the pillar in which the base region 17 is formed, the base region 17 becomes further large. Thus, the operation characteristic of the pillar bipolar transistor is lowered.
Additionally, since the emitter and collector regions must be formed at an upper portion of the pillar, there arises the problem that it is extremely difficult to perform a self-aligned contact open process.